The present invention relates to a time counting circuit for measuring such time as the pulse spacing of a pulse signal and to a method of generating a plurality of pulse signals.
There have been rising hopes for the use of time counting circuits for measuring such time as the pulse spacing of a pulse signal in the field of digital communication and the like. In recent years, it has become possible to mount a time counting circuit composed of a CMOS transistor in conjunction with other digital circuits on a single chip, which has accomplished a significant reduction in the cost of manufacturing semiconductor devices.
A time counting circuit which exhibits further stabilized operation with higher accuracy may also find extensive application in various fields including the demodulation of FM signals and the demodulation of bus signals in an LSI. Because of its capability of measuring extremely short time with accuracy and stability, the use of the time counting circuit for greatly reducing the number of buses in the LSI is particularly awaited.
FIG. 18 illustrates a structure of a conventional time counting circuit, in which are shown: an inverter ring 51; a row of holding circuits 52; signal converting means 53; time-difference operating circuit 54; a counter 55a; and a counter-output holding circuit 55b. A pulse signal to be measured is inputted to a pulse-signal input terminal and data representing the pulse spacing of the inputted pulse signal is outputted from an operation-result output terminal.
The time counting circuit shown in FIG. 18 includes the inverter ring 51 composed of a plurality of delay circuits each consisting of two inverters and one delay circuit consisting of three inverters (the final delay circuit in FIG. 18), which are connected in a ring configuration. Since the inverter ring 51 is composed of an odd number of inverters, so-called oscillation is observed whereby one signal transition occurs after another as though seemingly moving along the inverter ring 51 with the passage of time, resulting in circulations around the inverter ring 51. Therefore, time can be measured by examining variations in the output voltages from the individual delay circuits.
On the rising edge of the pulse signal to be measured, output signals from the individual delay circuits composing the inverter ring 51 are held in flip-flops (FFs) composing the row of holding circuits 52 and outputted to the signal converting means 53, which converts the output signals from the row of holding circuits 52 to data and outputs it to the time-difference operating circuit 54. The counter 55a counts the number of circulations of signal transition around the inverter ring 51 and outputs count data to the time-difference operating circuit 54 via the counter-output holding circuit 55b (see "Time-to-Digital Converter LSI" Technical Report of IEICE, ICD93-77 (1993-08)).
However, the conventional time counting circuit has the following disadvantages.
To cause oscillation in the inverter ring, an odd number of inverters should necessarily be provided therein. To implement a signal processing circuit of simple structure, a power-of-two number of delay circuits are preferably included in the inverter ring. Accordingly, the inverter ring comprises delay circuits of different structures in the conventional time counting circuit, as shown in FIG. 18.
In this case, however, it is difficult to equalize signal delay times in the individual delay circuits composing the inverter ring. Even if the inverter ring is designed so that signal delay times in the individual delay circuits become equal, signal delay times may vary differently in the delay circuits of different structures when a power-source voltage varies.
To eliminate the disadvantages, there can be proposed a method wherein time counting is performed by regarding one inverter as one delay circuit. In accordance with the method, holding circuits are connected to the respective output terminals of the inverters composing the inverter ring and output signals from the individual holding circuits are used to perform time counting.
FIG. 19(a) shows transitions of respective output signals from an odd number of identical inverters composing an inverter ring. In the drawing, it is assumed that the output signal from the 2nd inverter falls after the time t.sub.1 elapsed from the rising edge of the output signal from the 1st inverter. In short, a delay time in the 2nd inverter is indicated by t.sub.1. Likewise, respective delay times in the 3rd to 7th inverters are indicated by t.sub.2 to t.sub.6.
It is assumed here that a pulse signal to be measured rises at the time T.sub.1. At that time, the logic levels of the output signals from the 1st and 2nd inverters are HIGH successively. It is also assumed that the pulse signal to be measured rises again at the time T.sub.2. At that time, the logic levels of the output signals from the 6th and 7th inverters are LOW successively. From the foregoing description, it will be understood that signal transition circulating around the inverter ring has advanced from the 1st inverter to the 6th inverter during the period between the times T.sub.1 and T.sub.2.
The time required by signal transition to advance from the 1st inverter to the 6th inverter can be obtained by adding up respective delay times in the 2nd to 6th inverters, which is given by (t.sub.1 +t.sub.2 +t.sub.3 +t.sub.4 +t.sub.5). Hence, the time (T.sub.2 -T.sub.1) representing the pulse width is given by (t.sub.1 +t.sub.2 +t.sub.3 +t.sub.4 +t.sub.5). If each of the delay times in the individual inverters is assumed to be 1 ns, t.sub.1 =t.sub.2 =t.sub.3 =t.sub.4 =t.sub.5 =1 ns are satisfied so that the time (T.sub.2 -T.sub.1)=5 ns is satisfied.
The duration of time recognized as the time T.sub.1 by the inverter ring is equal to the delay time t.sub.1 in the 2nd inverter. The duration of time recognized as the time T.sub.2 by the inverter ring is equal to the delay time t.sub.6 in the 7th inverter. When the delay times in the individual inverters are equal, therefore, the pulse width can be measured by using the delay times as increments of time.
In practice, however, it is not necessarily easy to equalize the delay times in the individual inverters partly because the rise time of the output signal from the inverter is not necessarily equal to the fall time thereof.
If the inverter is composed of a CMOS inverter, the adjustment of the threshold voltage of the PMOS transistor and the adjustment of the threshold voltage of the NMOS transistor are performed in different processes. On the other hand, the rise time of the output voltage from the inverter is mainly determined by the threshold voltage of the PMOS transistor, while the fall time of the output voltage from the inverter is mainly determined by the threshold voltage of the NMOS transistor. Thus, different rise and fall times of the output voltage from the inverter, which is a common phenomenon, results from the manufacturing process.
FIG. 19(b) illustrates different delay times in the individual inverters when the rise time of the output signal from the inverter is different from the fall time thereof. In the drawing, the horizontal axis indicates time, the vertical axis indicates voltage, the voltage V.sub.DD indicates power-source voltage, and the voltage V.sub.T indicates the threshold voltage of each of the holding circuits connected to the individual inverters. The solid lines on the graph indicate transitions of the output signals from the individual inverters composing the inverter ring. The numeric characters accompanying the rising and falling edges on the graph indicate the stages of the inverters. The holding circuit holds an input voltage higher than the threshold voltage V.sub.T as a logic level "1", while holding an input voltage lower than the threshold voltage V.sub.T as a logic level "0".
As shown in FIG. 19(b), when the fall time of the output signal from the inverter is longer than the rise time thereof, the delay times t.sub.1, t.sub.3, and t.sub.5 are longer than 1 ns and the delay times t.sub.2, t.sub.4, and t.sub.6 are shorter than 1 ns.
If t.sub.1 =t.sub.3 =t.sub.5 =1.5 ns and t.sub.2 =t.sub.4 =t.sub.6 =0.5 ns are assumed to be satisfied, the duration of time recognized as the time T.sub.1 is 1.5 ns and the duration of time recognized as the time T.sub.2 is 0.5 ns, which indicates that the accuracy of time measurement is not constant.
Even if an inverter ring with equal rise time and fall time can be manufactured, the threshold voltage of the holding circuit varies with variations in power-source voltage and in temperature, so that the delay times in the individual inverters are not equal. To eliminate the problem, means for controlling the inverter ring by detecting variations in power-source voltage and in temperature should be provided in a time counting circuit, which increases circuit size and power consumption accordingly.